1. Field of the Invention
The present invention relates generally to inductor structures employed within microelectronic fabrications. More particularly, the present invention relates to planar spiral inductor structures employed within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are fabricated from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels and functionality levels have increased, it has become common in the art of microelectronic fabrication to employ in addition to generally conventional microelectronic device structures such as but not limited to transistor structures, resistor structures, diode structures and capacitor structures when fabricating microelectronic fabrications, less conventional microelectronic device structures such as inductor structures when fabricating microelectronic fabrications. In particular, within microelectronic fabrications which are intended to be employed within high frequency microelectronic fabrication applications, such as mobile communications high frequency microelectronic fabrication applications, it is often common to employ microelectronic inductor structures in conjunction with microelectronic capacitor structures within those microelectronic fabrications.
While microelectronic inductor structures, and in particular microelectronic inductor structures in conjunction with microelectronic capacitor structures, are thus desirable and often essential within the art of microelectronic fabrication, microelectronic inductor structures, and in particular microelectronic inductor structures in conjunction with microelectronic capacitor structures, are nonetheless not entirely without problems in the art of microelectronic fabrication. In that regard, it is typically desirable in the art of microelectronic fabrication, but nonetheless not always readily achievable in the art of microelectronic fabrication, to fabricate microelectronic fabrications having formed therein microelectronic inductor structures, and in particular microelectronic inductor structures in conjunction with microelectronic capacitor structures, with optimal performance while occupying minimal microelectronic substrate area within a microelectronic fabrication.
It is thus towards the goal of fabricating within microelectronic fabrications microelectronic inductor structures, and in particular microelectronic inductor structures in conjunction with microelectronic capacitor structures, with optimal performance while occupying minimal microelectronic substrate area within a microelectronic fabrication, that the present invention is directed.
Various microelectronic inductor structures having desirable properties, and/or methods for fabrication thereof, have been disclosed in the art of microelectronic fabrication.
For example, Yamaguchi et al., in “Characteristics and Analysis of a Thin Film Inductor With Closed Magnetic Circuit Structure,” IEEE Trans. on Magnetics, Vol. 28(5), Sep. 1992, pp. 3015–17, discloses for use within a microelectronic fabrication a planar spiral inductor structure with enhanced inductance. The planar spiral inductor structure realizes the foregoing object by employing when fabricating the planar spiral inductor structure a patterned copper core layer which is fully encapsulated with a magnetic material layer which contacts the patterned copper core layer, to provide surrounding the patterned copper core layer a closed magnetic circuit which provides the planar spiral inductor structure with enhanced inductance.
In addition, Shiga, in U.S. Pat. No. 5,396,101, discloses a planar spiral inductor structure for use within a microelectronic fabrication, where the planar spiral inductor structure may be formed while occupying minimal microelectronic substrate area within the microelectronic fabrication while providing the planar spiral inductor structure with enhanced inductance within the planar spiral inductor structure. To realize the foregoing objects, the planar spiral inductor structure employs a core layer formed of a high permeability magnetic material formed within a cavity within the planar spiral inductor structure, wherein the core layer may further be patterned to form a grid of electrically insulated patterned core layers.
Further in addition, Staudinger et al., in U.S. Pat. No. 5,481,131, discloses an integrated circuit microelectronic fabrication having fabricated therein a planar spiral inductor structure in conjunction with a planar capacitor structure, wherein there is minimized the use of substrate area when fabricating the planar spiral inductor structure in conjunction with the planar capacitor structure within the microelectronic fabrication. To realize the foregoing object, portions of the planar spiral inductor structure and the planar capacitor structure are fabricated employing a single patterned conductor layer, wherein the single patterned conductor layer is patterned to provide a planar spiral inductor which is surrounded by a capacitor plate employed within the planar capacitor.
Yet further, Ho et al., in U.S. Pat. No. 5,839,184, discloses a method for fabricating, while minimizing use of substrate area and while providing enhanced performance, an inductor structure within a packaged integrated circuit microelectronic fabrication. To realize the foregoing objects, the method employs when fabricating the packaged integrated circuit microelectronic fabrication at least one lead within a lead frame employed for packaging an integrated circuit microelectronic fabrication die as an inductor core within an inductor which accesses a bond pad within the integrated circuit microelectronic fabrication die which is packaged, and further wherein a bond wire which is bonded to the bond pad within the integrated circuit microelectronic fabrication die is employed as an inductor winding for the lead which serves as the inductor core.
Still further, Zhao et al, in U.S. Pat. No. 5,861,647, discloses an inductor structure or a capacitor structure which may be fabricated with enhanced efficiency within a microelectronic fabrication. Each of the inductor structure and the capacitor structure comprises a metal plug layer filled into a via which separates a pair of metal layers within the microelectronic fabrication, wherein the length of the metal plug layer is the same as the length of the pair of metal layers within the microelectronic fabrication, but wherein the width of the metal plug layer is less than the width of the pair of metal layers within the microelectronic fabrication.
Still yet further, Lue et al., in U.S. Pat. No. 5,863,806, discloses a method for fabricating within a semiconductor integrated circuit microelectronic fabrication a microcoil structure which may be employed for forming an inductor structure within the semiconductor integrated circuit microelectronic fabrication. To realize the foregoing object, the microcoil structure is fabricated employing a series of geometrically parallel conductively doped regions within a semiconductor substrate, wherein the series of geometrically parallel conductively doped regions within the semiconductor substrate is separated by a dielectric layer through which is formed a series of vias which provides access for a series of geometrically parallel patterned conductor layers which connect with the series of geometrically parallel conductively doped regions to form the microcoil structure within the semiconductor integrated circuit microelectronic fabrication.
Yet still further, Ramakrishnan et al., in U.S. Pat. No. 5,915,188, discloses a method for fabricating, with both enhanced inductance and enhanced capacitance within a microelectronic fabrication, a microelectronic inductor structure in conjunction with a microelectronic capacitor structure within the microelectronic fabrication. To realize the foregoing object the method employs forming a single patterned conductor layer which is patterned to form both: (1) a planar spiral within a planar spiral inductor which is employed for forming the microelectronic inductor structure; and (2) a planar capacitor plate within a planar capacitor employed for forming the microelectronic capacitor structure, in conjunction with a copper-iron alloy oxide dielectric layer which passivates the planar spiral within the planar spiral inductor and serves as a capacitor dielectric layer within the planar capacitor.
Finally, Kato et al., in U.S. Pat. No. 5,945,892, discloses a microelectronic fabrication having fabricated therein a microelectronic inductor structure in conjunction with a microelectronic capacitor structure, but wherein there is avoided within the microelectronic inductor structure in conjunction with the microelectronic capacitor structure eddy current losses. To realize the foregoing object, the microelectronic fabrication employs when fabricating the microelectronic inductor structure a conductor inductive element which is generally perpendicular to a pair of capacitor plate layers within a planar capacitor which comprises the microelectronic capacitor structure.
The teachings of each of the foregoing disclosures are incorporated herein fully by reference.
Desirable in the art of microelectronic fabrication are additional methods and materials which may be employed for fabricating within microelectronic fabrications microelectronic inductor structures, and in particular microelectronic inductor structures in conjunction with microelectronic capacitor structures, with optimal performance while occupying minimal microelectronic substrate area within a microelectronic substrate which is employed for fabricating the microelectronic inductor structure, and more particularly the microelectronic inductor structure in conjunction with the microelectronic capacitor structure.
It is towards the foregoing objects that the present invention is directed.